Intel Standard Cell Architecture Pathfinding and Definition Lead in Topeka, Kansas
Advanced Design Group under Design Enablement in Technology Development has primary focus of Design-Technology Co-optimization (DTCO) and Foundational IP development to support both the Technology Development organization and Intel's IP/Product design teams. Advanced power, performance, and area (PPA) analyses are conducted across domains to guide Technology Development's research, pathfinding, and technology definition.
Library Technology Group in Advanced Design is looking for a highly motivated and experienced individual to lead the pathfinding, development, and optimization of standard cell libraries to enable best-in-class IP and product design on all generations of Intel technology.
As a technical lead, you are responsible for leading the standard cell architecture pathfinding activities with active collaboration with process technologists, product design stake holders, and EDA vendors to achieve best-in-class cell/block level PPA and competitive EoU (Ease of Use) through DTCO.
Other responsibilities include (but not limited to) supporting test-chip planning and Si validation of standard cells to track yield, Vmin and power/performance.
Successful experience in leading std cell library pathfinding and definition to optimize PPA through DTCO on advanced technology nodes strongly preferred
In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction, and characterization highly desired
Experience in EDA tool/flow/methodology, product, and IP developments
Familiar with foundry ecosystem and benchmarking practice
Excellent communication and interpersonal skills to champion initiatives internally and externally, and drive effective communication with executive management and external partners
Technical, analytical, and cross-functional collaboration skills
Ability to work in a dynamic and team-oriented environment
Strong independence and proven ability to set and meet own goals
Experience working with external leading edge foundry process nodes
Extensive experience working with EDA vendors to drive new features and capabilities
Experience in the development of design automation tools/flows, programming skills
Strong knowledge of industry-standard EDA tools for VLSI circuit and layout design
Good engineering acumen and analytical skills. Quick learner with debugging
Customer oriented and able to work in a dynamic environment
MS or Ph.D. in Electrical Engineering, Computer Science, Computer Engineering, or other related field of study
Minimum of 10 years of experience in foundational IP pathfinding in DTCO, silicon implementation, or technology development
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $180,270.00-$288,770.00
*Salary range dependent on a number of factors including location and experience
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.